In terms of improvement in bit density of a nonvolatile semiconductor memory device such as a NAND-type flash memory, stacking of memory cells is desired since a miniaturizing technique is about to reach the limit. As an example thereof is proposed a stacked NAND-type flash memory constructing memory transistors with use of vertical transistors. The stacked NAND-type flash memory has a memory string containing a plurality of memory transistors connected in series in a stacking direction and selected transistors provided on both ends of the memory string.
In this stacked NAND-type flash memory, for the purpose of decreasing a circuit area of a peripheral circuit such as a row decoder, a structure in which a plurality of memory strings arranged in a matrix form are connected in common to one word line is adopted. The plurality of memory strings sharing the word line constitute a memory block, which is a minimum unit at the time of data erasure. Thus, in the stacked NAND-type flash memory, as the stacking number increases, the size of one memory block increases, which causes the minimum unit for data erasure to be larger. Making the minimum unit for data erasure smaller substantially means decreasing a data storage capacity, which is not favorable. Accordingly, development of a stacked flash memory enabling only a part of memory cells in one memory block to be erased selectively is desired.